module sim12_mem( input  clk, memwrite,
            input  [7:0] a,
            input [11:0] wd,
            output [11:0] rd);

  reg  [11:0] RAM[255:0];


initial
    begin
      $readmemh("test_data.dat",RAM);
    end

assign rd = RAM[a];

always @(posedge clk)
  begin    
    if (memwrite)
      RAM[a] <= wd;
  end
endmodule
